STKALIGN=VALUE_0, UNALIGN_TRP=VALUE_0
Configuration and Control Register
| NONBASETHRDENA | Indicates how processor enters Thread mode |
| USERSETMPEND | Enables unprivileged software access to STIR register |
| UNALIGN_TRP | Enables unaligned access traps 0 (VALUE_0): Do not trap unaligned halfword and word accesses 1 (VALUE_1): Trap unaligned halfword and word accesses |
| DIV_0_TRP | Enables divide by 0 trap |
| BFHFNMIGN | Ignore LDM/STM BusFault for -1/-2 priority handlers |
| STKALIGN | Indicates stack alignment on exception entry 0 (VALUE_0): 4-byte aligned 1 (VALUE_1): 8-byte aligned |